The present invention relates generally to techniques for addressing computer memory storage cells. More particularly, the invention relates to memory storage addressing, in direct memory access (DMA) operations wherein a plurality of computer processors or other devices may be connected to a single data bus or Input/Output (I/O) channel, and wherein one processor may directly access the storage media of another processor for transfer of data over the bus. The present invention may also be employed in other protocols and interconnection media such as those for serial, fiber-optic interconnection media, both shared and switched, to impart the general advantages of DMA mechanisms to these media. In the context of the present disclosure it is to be understood that terms such as "DMA," "DMA bus" and "communication bus" refer to both prior art DMA systems and all other applicable protocols and media.
The features of the invention relate generally to the implementation of storage reference and data description protocols on a shared medium, such as a data bus or channel, for the interconnection of processing and peripheral device elements. More specifically, the invention describes an improved method of specifying storage buffers by one such element to the storage of another, target element.
The invention eliminates one of the prior art difficulties with DMA, i.e., dependencies on the storage architecture of those elements performing DMA operations, while preserving the benefits of the DMA concepts in general.
Direct memory access (DMA) protocols are well known in the prior art, and are characterized by the presence of a DMA "port" facility which directly references the storage of one or both of two communicating elements, as a part of the normal operating protocols of the interconnection medium between these elements, to effect the transfer of a portion of data from one element to the other. The DMA "port" facility may be a component of one or both communicating elements, or may be a distinct third entity which may concurrently reference the storage of one or both elements. A primary characteristic in the prior art is that the DMA "port" facility uses real storage addresses defined within the scope of one or both elements. This has the consequence that the DMA "port" facility must be implemented and specifically adapted to the storage architectures of the elements whose storage it references. This limitation introduces the need for that entity which manages the operation of a DMA "port" to have explicit knowledge of the physical organization of data in those elements referenced by that DMA "port."
An additional characteristic of the prior art is that the specification of the storage location of data within one or both communicating elements must be synchronous with respect to the transfer of data over the interconnection medium associated with the storage locations. This becomes a disadvantage whenever there is a latency period between the data specification and the data transfer phases of the DMA operation, because this produces an idle period on the interconnection medium that reduces its utilization during the DMA operation, and in the fact that other elements sharing the interconnection medium may not utilize the medium during the latency period. This latency results as a consequence of the internal processing and storage access delays during the data specification phase at the target element, or as a result of propagation delays of data specification or data itself on the interconnection medium. The latter delay is particularly significant in high band-width, serial fiber-optic interconnection mediums, in which long distances between elements are possible and which lead to propagation latencies on the interconnection medium that are very large with respect to the signaling frequency of the medium.
The present invention alleviates the disadvantages in the prior art, by providing an alternate technique of data specification in which the DMA "port" facility does not require explicit knowledge of either the storage architecture or the data organization within the target element of a DMA operation. Secondly, the present invention describes the data specification and data transfer phases of the DMA operation such that each may proceed as a discrete operation on the interconnection medium, asynchronous to the other. This asynchronism allows higher utilization of the interconnection medium both by permitting other elements to communicate during the latency period between the data specification and data transfer phases, and by allowing the communicating elements to interleave multiple data specification and data transfer phases.